Over deze vacature
For our semiconductor client in Nijmegen, Netherlands we are looking for a Senior AMS Verification Engineer
To support R&D projects, an SLA (Service-Level Agreement) Team has been setup within our client, located in Nijmegen/Eindhoven for new product development. The SLA team consists mainly of IC and System Architects, IC designers, test and product as well as quality/reliability engineers.
- Define AMS verification strategy, develop verification plans;
- Develop mixed signal models for analog circuits, run unit tests for mode validation;
- Execute mixed signal verification according the verification plan;
- Document verification results;
- Develop production test vectors;
- Support test engineers and IC design engineers;
- Participate in design reviews;
- Schedule tasks and report progress to project leader.
Headquartered in Nantong, China, near Shanghai, Datang our client is a fabless semiconductor company serving the automotive market, with R&D (research & development) and Sales & Marketing operations located in Shanghai. The company primarily serves the domestic Chinese market, focusing on research, development and sale of advanced application specific automotive products in Analog Mixed Signal technology, in the same time addresses as well as relevant segments of the global market. NXP holds a 49% share in the JV, with China DatangTelecom holding 51%.
- Good employee benefits (e.g. work-life balance, pension, lease car, bonus model);
- Challenging assignments;
- Excellent guidance from your consultant and YER's back office;
- Development opportunities, including the YER Talent Development Programme with a personal coach;
- Intensive support for international candidates (including Dutch lessons, tax-return and accommodation assistance);
- Cooperative and results and relationship-driven;
- Friendly atmosphere and open culture;
- Community/network with other technology professionals from a variety of multinationals;
- Events and master classes with interesting speakers and attractive companies.
- MSc (preferred) or BSc degree in analog design, more than 10 years of working experience;
- Must: Knowledge of modelling languages (Verilog A, Verilog AMS, System Verilog);
- Must: Knowledge of programming languages (C++, Visual Basic, SKILL);
- Must: Knowledge of analogue circuit design, semiconductor devices and relevant CAD tools;
- Must: Experience with WREAL modelling and UVM method and tools;
- Sound electrical engineering knowledge in analog and digital including IPs such as ADC, DAC, PLLs, LDOs, DCDC converters and amplifiers;
- Very good English language skills;
- Capable of working in a multi-culture environment, communications skills, willing to travel to Fareast (a few times a year, max stay 2-3 weeks).
Next to the technical skills, the following inter-personal skills are equally important:
- Communication skills, especially with engineers who do not master English well;
- Awareness working in a multi-culture environment;
- Travel to Shanghai, minimum 4 times/year, duration 2 weeks each time.