Design Verification Engineer

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  • Aanbod Good Remuneration
  • Functiegroep Engineering
  • Dienstverband Fulltime
  • Vacaturenummer 9347900
  • Locatie Hamburg
  • Contract Detachering via YER
  • Branche High Tech

Over deze vacature

For our top semiconductor client in Germany, we are looking for a Design & Verification Engineer

Functie

The role is part of the hardware design team in the Secure Mobile Transactions business within our client. This team is tasked with delivering high quality solutions for mobile transactions (Secure Elements, NFC) to demanding mobile customers.

• Deep understanding of Metric driven verification, functional and code coverage
• Experience with UVM
• Proficient in the languages used for testcase development, especially Verilog, and System Verilog. C is nice to have
• Understanding of directed and constrained random methodologies
• Experience in Testbench design with standard verification frameworks like UVM/OVM
• Knowledge and experience of formal verification methodologies and assertions
• Understanding of the architecture, elements and functionality of SOCs, including CPUs, DMA, MMU, PLLS, memory and peripheral interfaces
• Experience in verification of SOCs with significant analog content is a bonus
• Knowledge of product and IC/IP design processes
• Understanding of software development process for embedded CPUs and experience in developing and debugging software
• Expertise in the use of EDA tools for the developement, simulation and debug of functional tests (RTL simulators, C compilers, debuggers )
• Experience with debug on designs pre and post-silicon, in simulation and on the bench
• Degree in Engineering with 5+ years of experience

Bedrijf

Semiconductor company in Austria

Aanbod

  • Good employee benefits (e.g. work-life balance, pension, lease car possible, bonus model)
  • Challenging assignments
  • Excellent guidance from your consultant and YER's back office
  • Development opportunities, including the YER Talent Development Programme with a personal coach
  • Intensive support for international candidates (including Dutch lessons, tax-return and accommodation assistance)
  • Cooperative and results and relationship-driven
  • Friendly atmosphere and open culture
  • Community/network with other technology professionals from a variety of multinationals
  • Events and master classes with interesting speakers and attractive companies

Profiel

• Deep understanding of Metric driven verification, functional and code coverage
• Experience with UVM
• Proficient in the languages used for testcase development, especially Verilog, and System Verilog. C is nice to have
• Understanding of directed and constrained random methodologies
• Experience in Testbench design with standard verification frameworks like UVM/OVM
• Knowledge and experience of formal verification methodologies and assertions
• Understanding of the architecture, elements and functionality of SOCs, including CPUs, DMA, MMU, PLLS, memory and peripheral interfaces
• Experience in verification of SOCs with significant analog content is a bonus
• Knowledge of product and IC/IP design processes
• Understanding of software development process for embedded CPUs and experience in developing and debugging software
• Expertise in the use of EDA tools for the developement, simulation and debug of functional tests (RTL simulators, C compilers, debuggers )
• Experience with debug on designs pre and post-silicon, in simulation and on the bench
• Degree in Engineering with 5+ years of experience

Personal Traits

• Flexible and adaptable with an ability to verify and debug at many levels and on many different platforms
• Rigourous and methodical with good analytical skills
• Pays attention to details, tenacity in tracing and finding problems
• Ability to question and identify weaknessess in written specifications
• Good team player with ability to work across teams and sites

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