Detachering via YER
Medical & Health
Over deze vacature
At Philips Research a project is ongoing for the design of a mixed-signal IC for biomedical applications.
The SOI-CMOS IC includes analog, digital and mixed-signal circuits. The candidate will contribute to thedesign of this IC.
With a growing presence in cardiology, oncology, and women's health, Philips operates in the areas of Imaging Systems, Patient Care & Clinical Informatics, Home Healthcare and Customer Services. Philips combines its clinical expertise and human insights to create innovative solutions across the continuum of care, in partnership with clinicians and our customers, to provide better value and expand access to care for millions. Our teams are working hard every day to improve patient outcomes all the way from disease prevention and screening to diagnosis, treatment, therapy monitoring, and disease management. Irrespective of whether the care cycle takes the patient from doctor's office to hospital or hospital to home, or simply from one medical department to another, Philips Healthcare's unique medical solutions are designed to optimize the quality and flow of patient information and clinical decision making.
- You will be employed by YER and seconded to Philips;
- Good employee benefits (e.g. work-life balance, pension);
- Development opportunities, including the YER Talent Development Programme with a personal coach;
- Intensive support for international candidates (including Dutch lessons, tax-return and accommodation assistance);
- Cooperative and results and relationship-driven;
- Community/network with other technology professionals from a variety of multinationals;
- Events and master classes with interesting speakers and attractive companies.
The candidate must meet the following minimum requirements:
- At least five years of experience in analog circuit design, simulation and layout using Cadence. Designing circuits such as amplifiers, buffers, current sources, etc.
- Understanding of CMOS technologies in general: working with design rules, understanding process specification documents
- Creating simulation test-benches for dc, ac, transient simulations using ADE-L and ADE-XL
- Understanding low-noise analog circuit design
- Familiar with CMOS technologies at various technology nodes such as 180nm to 40nm
- Experience with SOI-CMOStechnologies is beneficial
- Basic knowledge of MatLab. Experience with Cadence-MatLab co-simulation is a plus
- Experience with full-custom IC layout design using Cadence tools Virtuoso, Layout-XL, DRC and LVS
- Understanding and implementing layout techniques such as symmetry and shielding
- Creating layout designs according to a floorplan
- Basic understanding of Unix
- Team player: daily interaction with designteam
- Reporting progress and issues
- Fluent in English
- Experience with mixed-signal design and verification using AMS is a plus
- Basic knowledge of digitaldesign / Encounter is beneficial