Detachering via YER, In dienst van opdrachtgever
Over deze vacature
For Nexperia's Logic products we are on the lookout for a Layout Engineer.
In this exciting role, you are responsible for the delivery of fully verified layout designs (full custom), which meets all technical requirements provided by the designer. The main aspects in the standard analog based design flow are floor planning, transistor level layout and placement of IP, manual routing, full chip verification by DRC, LVS, ERC, package assembly rules and ESD/LU guidelines. This is all done in a Cadence design environment combined with appropriate tool and sub-micron process knowledge.
Nexperia is a dedicated global leader in Discretes, Logic and MOSFETs devices. They are a new company with a long history, broad experience and a global customer base. Originally part of Philips, they became a business unit of NXP before becoming an independent company in the beginning of 2017. Nexperia’s focus remains on efficiency, producing consistently reliable semiconductor components at high volume: 85 billion annually. They have an extensive portfolio, produced to meet the stringent standards set by the Automotive industry. Their industry-leading small packages, produced in-house, combine power and thermal efficiency with best-in-class quality levels.
You will be employed by YER and seconded to Nexperia. YER offers competitive compensation. A, more than, comfortable package will be provided to the suitable candidate. If necessary YER will arrange a valid VISA for you and your family as offer guidance towards settling in The Netherlands. Depending on experience and education higher remuneration is possible. Moreover, we provide attractive benefits to our employees.
We are an Equal Opportunity Employer and do not discriminate against any employee or applicant for employment because of race, colour, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any other federal, state or local protected class.
- Bachelor degree in Electronic Engineering
- 3+ year experience in Transistor Level IP and I/O Layout
- Skilled on with Cadence, Dracula and Assura Layout tooling
- Owns basic knowledge of Electro Static Discharge and Latch-Up mechanisms
- Experienced in submicron C100–like processes of the Semiconductor industry
- Good communication skills in both Dutch and English
- Target driven, shows initiative and can work independently